Tutorial 10: Peripheral 2 - Nested Vector Interrupt controller (NVIC) in STM32
Nested Vector Interrupt controller (NVIC) in STM32
▶️Nested Vector Interrupt Controller (NVIC) is a dedicated controller embedded inside the MCU to manage all the System and Peripheral exceptions.
It’s main application involves dynamic prioritization of the interrupt levels, fast response to the interrupt requests due to low latency response and tail chaining as well as from vector table relocation.
▶️The NVIC is an integral part of all Cortex-M processors and provides the outstanding interrupt handling abilities.
▶️NVIC includes the following features:
➡️52 maskable interrupt channels in STM32F401xE and 91 maskable interrupts channels in STM32F42xxx (not including 16 interrupt lines of Cortex-M4 with FPU).
➡️16 programmable priority levels (4 bits of interrupt priority are used)
low-latency exception and interrupt handling as the NVIC and the processor core interface are closely coupled.
➡️power management control and efficient processing of late arriving interrupts.
implementation of system control registers.
➡️number of maskable interrupt channels will vary based on MCU core
✔ Register for this free course & you will get an access to e-Learning content and code files🏆🚀
https://www.hexnbit.com/product/free-...
🌐 STM32 Related Courses:
Certificate Course: https://www.hexnbit.com/advance-embed...
Foundation Course: https://www.hexnbit.com/product/found...
✨ HEXNBIT Social Media :
Instagram: / hexnbit
Twitter: / hexnbit_life
YouTube: / hexnbit
Facebook: / hexnbit
🎓 Other Courses:
Visit : https://www.hexnbit.com/
About us: Hexnbit provides one-stop solutions for the students & working professionals in Skill development programs. The platform not only provides subject expertise to the candidates but also, give them industry exposure to apply their learnings analytically in a practical real-world.